Freescale Semiconductor /MKW20Z4 /XCVR /TSM_TIMING15

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TSM_TIMING15

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI 0PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO

Description

TSM_TIMING15

Fields

PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI

Assertion time setting for PLL_TX_LDV_RIPPLE_MUX_EN TX sequence.

PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO

Deassertion time setting for PLL_TX_LDV_RIPPLE_MUX_EN signal or group TX sequence.

Links

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